The present invention relates to semiconductor device manufacturing, and more particularly to methods and apparatus for forming barrier layers in high aspect ratio vias employed within semiconductor devices.
A typical integrated circuit contains a plurality of metal pathways that provide electrical power to the various semiconductor devices forming the integrated circuit, and that allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or xe2x80x9cinterlayerxe2x80x9d dielectrics that insulate the metal layers from each other.
Generally, each metal layer must form electrical contact to at least one additional metal layer. Such metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and by filling the resulting via with a metal to create an interconnect as described further below. Metal layers typically occupy etched pathways or xe2x80x9clinesxe2x80x9d in the interlayer dielectric. For simplicity, as used herein, the term xe2x80x9cviaxe2x80x9d refers to any feature such as a hole, line or other similar feature formed within a dielectric layer that assists in establishing an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer.
Because copper has a lower resistivity than aluminum, copper metals layers and interconnects have gained popularity in contrast to more conventional aluminum metal layers and interconnects. Copper atoms, however, are highly mobile in silicon dioxide and may create electrical defects in silicon. Accordingly, copper metal layers and copper interconnect vias conventionally are encapsulated with a barrier material (e.g., to prevent copper atoms from creating leakage paths in silicon dioxide or similar interlayers and/or defects in the silicon substrate on which the copper layers and interconnects are formed).
Barrier layers typically are deposited on via sidewalls and bottoms prior to copper seed layer deposition, and may include materials such as tungsten, titanium, tantalum, nitrides thereof, etc. Tantalum nitride is particularly popular due its lower resistivity and favorable adhesion properties.
As is well known, an increase in device performance is typically accompanied by a decrease in device area or an increase in device density. An increase in device density requires a decrease in the via dimensions used to form interconnects (e.g., a larger depth-to-width ratio or a larger xe2x80x9caspect ratioxe2x80x9d). As via dimensions decrease, and aspect ratios increase, forming adequately thick and uniform barrier layers on the sidewalls of vias has become difficult. This problem is exacerbated within low K dielectric interlayers, as sidewall barrier layers often serve the additional role of providing mechanical strength to such low K dielectric interlayers.
Accordingly, a need exists for improved methods and apparatus for forming barrier layers in high aspect ratio vias.
In first, second and third embodiments of the invention, methods are provided for forming a barrier layer on a substrate having a metal feature, a dielectric layer formed over the metal feature, and a via having sidewalls and a bottom. The via extends through the dielectric layer to expose the metal feature.
In the first embodiment, a method includes forming a barrier layer over the sidewalls and bottom of the via using atomic layer deposition. The barrier layer has sufficient thickness to serve as a diffusion barrier to at least one of atoms of the metal feature and atoms of a seed layer formed over the barrier layer. The method further includes removing at least a portion of the barrier layer from the bottom of the via by sputter etching the substrate within a high density plasma physical vapor deposition (HDPPVD) chamber having a plasma ion density of at least 1010 ions/cm3 and configured for seed layer deposition. A bias is applied to the substrate during at least a portion of the sputter etching. The method also includes depositing a seed layer on the sidewalls and bottom of the via within the HDPPVD chamber.
In the second embodiment, the method includes forming a first barrier layer over the sidewalls and bottom of the via using atomic layer deposition. At least a portion of the first barrier layer is removed from the bottom of the via by sputter etching the substrate within a high density plasma physical vapor deposition (HDPPVD) chamber having a plasma ion density of at least 1010 ions/cm3 and configured for depositing a second barrier layer. A bias is applied to the substrate during at least a portion of the sputter etching. The method also includes depositing a second barrier layer on the sidewalls and bottom of the via within the HDPPVD chamber.
In the third embodiment, the method includes the steps of (1) forming a first barrier layer over the sidewalls and bottom of the via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching the substrate; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects of the invention. Each computer program product described herein may be carried by a medium readable by a computer (e.g., a carrier wave signal, a floppy disc, a compact disc, a DVD, a hard drive, a random access memory, etc.).
Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.